Circuit micropatterning and an increase in density require a projection exposure apparatus for manufacturing a semiconductor device to project a circuit pattern formed on a reticle surface onto a wafer surface at a higher resolving power. The circuit pattern projection resolving power depends on the NA (Numerical Aperture) of a projection optical system and the exposure wavelength. The resolving power is increased by increasing the NA of the projection optical system or shortening the exposure wavelength. As for the latter method, the exposure light source is shifting from g-line to i-line, and further from i-line to an excimer laser. With the excimer laser, exposure apparatuses having oscillation wavelengths of 248 nm and 193 nm are available.
At present, a VUV (Vacuum Ultra Violet) exposure system with a shorter oscillation wavelength of 157 nm and an EUV (Extreme Ultra Violet) exposure system with a wavelength of 13 nm are examined as candidates for next-generation exposure systems.
Along with circuit micropatterning, demands have also arisen for aligning at a high precision a reticle on which a circuit pattern is formed and a wafer onto which the circuit pattern is projected. The necessary precision is one-third the circuit line width. For example, the necessary precision in a current 180-nm design is one-third, i.e., 60 nm.
In this situation, the exposure pattern overlay precision must be increased, and an increase in alignment precision is indispensable. The alignment method includes die-by-die alignment and global alignment. In die-by-die alignment, misalignment of an alignment mark is measured for each chip or shot. The misalignment is reduced to an allowance, and then exposure is executed. In global alignment, not all shots on a wafer are measured, but misalignment of several shots is measured, and a shot layout error on the wafer from the wafer stage coordinate system of an exposure apparatus is calculated. After that, the wafer is positioned at the precision of the wafer stage in accordance with the calculation result, and exposure is executed. Of these alignment methods, die-by-die alignment requires a large number of measurement operations, which is disadvantageous to throughput. Hence, global alignment advantageous to throughput is generally employed.
Various device structures have been proposed and examined for commercial use. With the spread of personal computers, and the like, micropatterning has shifted from memories such as a DRAM to CPU chips. For further IT revolution, micropatterning will be further advanced by the development of MMIC (Millimeter-wave Monolithic Integrated Circuits), and the like, used in communication system devices called a home wireless LAN and Bluetooth®, highway traffic systems (ITS: Intelligent Transport Systems) represented by a car radar using a frequency of 77 GHz, and wireless access systems (LMDS: Local Multipoint Distribution Service) using a frequency of 24 to 38 GHz.
There are also proposed various semiconductor device manufacturing processes. As a planarization technique which solves an insufficient depth of exposure apparatus, the W-CMP (Tungsten Chemical Mechanical Polishing) process has already been used. Instead, the Cu dual damascene process has received a great deal of attention.
Various semiconductor device structures and materials are used. For example, there are proposed a P-HEMT (Pseudomorphic High Electron Mobility Transistor) and M-HEMT (Metamorphe-HEMT), which are formed by combining compounds such as GaAs and InP, and an HBT (Heterojunction Bipolar Transistor) using SiGe, SiGeC, and the like.
Under the present circumstance of the semiconductor industry, many apparatus variables (=parameters) must be set in correspondence with each exposure method and each product in the use of a semiconductor manufacturing apparatus, such as an exposure apparatus. The number of parameters to be optimized is very large, and these parameters are not independent of each other, but are closely related to each other.
These parameter values have conventionally been decided by trial and error by the person in charge of introducing an apparatus of a device manufacturer. A long time is taken to decide optimal parameter values. If, e.g., a process error occurs after the parameter values are decided, the parameter values of the manufacturing apparatus must be changed again along with a corresponding change in the manufacturing process. Also, in this case, a long time is taken to set parameter values.
In the semiconductor device production, the time which can be taken until the start of volume production after the activation of a manufacturing apparatus is limited. The time which can be taken to decide a parameter value is also limited. In terms of CoO (Cost of Ownership), the operating time of the manufacturing apparatus must be prolonged. To change a parameter value which has already been decided, it must be quickly changed.
In this situation, it is very difficult to optimize parameter values for various semiconductor devices in a short time and manufacture various semiconductor devices with optimal parameter values. Even a manufacturing apparatus which can originally achieve a high yield can only exhibit a low yield because the apparatus is used without optimizing parameter values, resulting in a potential decrease in yield. Such a decrease in yield leads to a high manufacturing cost, a small shipping amount, and weak competitiveness.
Especially, in global alignment, which is generally adopted as the alignment method described above, only several shots (to be referred to as sample shots) on a wafer are measured. Measurement is greatly influenced by the stability of the alignment mark manufacturing process of the shots (for each wafer or each lot). The yield may decrease due to a low overlay precision depending on the lot. This disadvantage will become more conspicuous along with an increase in wafer diameter.